When scaling for next generation complementary metal-oxide semiconductor (CMOS) devices in connection with increased miniaturization, including, for example, very-large-scale integration (VLSI), middle-of-the-line (MOL) resistance can be a critical issue affecting device performance.
In conventional devices, increased MOL resistance can be caused by high-resistance interfaces between contact area (CA) metals and trench silicide (TS) regions. According to conventional processing, a liner that is needed for CA metallization, such as, for example, titanium nitride (TiN), has a high resistivity, and is positioned between a CA metal layer and a TS region. The liner, which is positioned as a high-resistance interface between the CA metal layer and a TS region, undesirably increases overall MOL resistance.
Accordingly, there is a need for a semiconductor device which does not include a high-resistance interface between the CA metal layer and a TS region and a method of manufacturing same.